List the types of FM detector. Explain any one of them.

1 Answer

Types of FM detector:-

1. Simple slope detector

2. Balanced slope detector

3. Phase discriminator(Foster seely discriminator)

4. Ratio detector

5. PLL detector

Simple slope detector:-


Explanation:- Consider a frequency modulated signal fed to a tuned circuit at primary and is tuned to frequency fc. The resonant frequency of secondary side tuned circuit is adjusted to (fc +∆f). The output pf this tuned circuit will have an amplitude that depends on the frequency deviation of the input signal. The circuit is detuned by an amount of ∆f, to bring the carrier centre frequency to required point on the selectivity curve. Frequency variations produces an output voltage proportional to the frequency deviations of the carrier. This output voltage is applied to a diode detector with RC load of suitable time constant which gives original modulating signal at output.  


Balanced slope detector:-


Explanation:- The circuit uses two slope detectors, connected back to back to the opposite ends of centre tapped transformer and hence fed 180 degree out of phase. The circuit is divided into three tuned circuits. Primary side tuned circuit is tuned to centre frequency fc and secondary side top of tuned circuit is tuned above IF i .e. (fc + ∆f) and bottom of tuned circuit is below IF i. e. (fc -∆f). Each tuned circuit is connected to diode detector and RC load.

R1C1 and R2C2 are filters to remove RF ripple.

The final output voltage Vo is

Vo = Vo1- Vo2

When fin = fc; Vo1 =Vo2, hence Vo =0v

When fc < fin<(fc+ f); Vo1> Vo2;that is Vo is positive

When (fc- f)< fin<fc; Vo2> Vo1; that is Vo is negative 


Circuit diagram of Foster Seely discriminator / detector:-


Working principle:- It uses a double-tuned RF transformer to convert frequency variations in the received fm signal to amplitude variations. These amplitude variations are then rectified and filtered to provide a dc output voltage. This voltage varies in both amplitude and polarity as the input signal varies in frequency. The output voltage is 0 when the input frequency is equal to the carrier frequency (FR). When the input frequency rises above the center frequency, the output increases in the positive direction. When the input frequency drops below the center frequency, the output increases in the negative direction. The output of the Foster-Seely discriminator is affected not only by the input frequency, but also to a certain extent by the input amplitude. Therefore, using limiter stages before the detector is necessary. Figure shows a typical Foster-Seely discriminator. The primary tank circuit consists of C1 and L1. C2 and L2 form the secondary tank circuit. Both tank circuits are tuned to the center frequency of the incoming fm signal. Choke L3 is the dc return path for diode rectifiers D1 and D2. Resistors R3 and R4 are the load resistors and are bypassed by C3 and C4 to remove radio frequency.

Circuit diagram of Ratio detector:-


Explanation:- With diode D2 reversed biased, point O is now positive with respect to b, so that Vab is now sum voltage. Large capacitor C5 is connected to keep the o/p sum voltage constant, even though the load current increases. Thus provides the amplitude limiting. Output voltage Vo is equal to half of the difference between the output voltages from the individual diodes. Thus output voltage is proportional to the difference between the individual output voltages. L3 matches the low impedance secondary to primary and provides voltage step down to prevent too great damping of primary by the ratio detector action. 

PLL detector:-


Explanation: 1. A PLL frequency demodulator requires no tuned circuits and automatically compensates for changes in the circuit frequency due to instability in the transmit oscillator. 2. Therefore, if the PLL input is a deviated FM signal and the VCO natural frequency is equal to the IF center frequency, the correction voltage produced at the output of the phase comparator and fed back to the input of the VCO is proportional to the frequency deviation. If the IF amplitude is sufficiently limited prior to reaching the PLL and the loop is properly compensated 

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