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Most microprocessors have a nonmaskable interrupt, an input pin that causes an interrupt that cannot be disabled.
If an interrupt routine shares any data with the task code, then it is necessary to disable that interrupt. Since we can not disable the non-maskable interrupts. Thus the associated ISR must not share any data with then task code.
Because of this, the non-maskable interrupts is most commonly used for events that are completely beyond the normal range of the ordinary processing.
For example, the Non-maskable interrupt might be used to allow your system to react to a power failure.
Some microprocessors use a different mechanism for disabling and enabling interrupts. These microprocessors assign a priority to each interrupt request signal and allow your program to specify the priority of the lowest priority interrupts that it is willing to handle at any given time.

Microprocessors can:
1. Disable all interrupts (except for then non-maskable interrupts)
2. It can enable all interrupts by setting the priority level.
3. It allows us to enable and disable individual interrupts.
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