search
person

1 Answer

Instruction execution has 5 basic stages:

1. Fetch instruction:

The task of reading the next instruction from memory into the instruction register.

2. Decode instruction:

The task of determining what operation the instruction on the instruction register represents. Ex. add, move

3. Fetch oprands:

The task of moving the instructions operands data into appropriate register.

4. Execute operation:

The task of feeding the appropriate registers through the ALU and back into an appropriate register.

5. Store results:

The task of writing a register into memory.

thumb_up_alt 0 like thumb_down_alt 0 dislike

Related questions

Description : AVR microcontroller executes most of the instruction in _________________. A. Single execution cycle. B. Double execution cycle. C. Both A& B D. None of the above.

Answer : A. Single execution cycle. 

Description : The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device is attached to the system while CPU executes the background programs continuously. What is the maximum IO data transfer rate if programmed IO data transfer technique is used? (A) 500 Kbytes/sec (B) 2.2 Mbytes/sec (C) 125 Kbytes/sec (D) 250 Kbytes/sec

Answer : (D) 250 Kbytes/sec

Description : A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register at the end of the fetch cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval

Answer : (A) by checking interrupt register after execution of each instruction

Description : If initial content of accumulator is 44 H, find out the new content of accumulator after execution of the instruction RR A

Answer : Contents of Acc will be 22H ( as RR A divides acc by 2)

Description : In an 8085 microprocessor, after the execution of XRA A instruction A) the carry flag is set B) the accumulator contains FFH C) the zero flag is set D) the accumulator contents are shifted left by one bit

Answer :  In an 8085 microprocessor, after the execution of XRA A instruction the zero flag is set 

Description : Which flag does not change by the execution of the instruction DCR B in 8085 microprocessor ?  (a) Parity (b) Carry (c) Zero (d) Sign

Answer : Which flag does not change by the execution of the instruction DCR B in 8085 microprocessor ?  (a) Parity (b) Carry (c) Zero (d) Sign

Description : A ______ Instruction at the end of interrupt service program takes the execution back to the interrupted program.   (a) Forward (b) Return (c) Data (d) Line 

Answer : A Return Instruction at the end of interrupt service program takes the execution back to the interrupted program.

Description : The Complement Accumulator (CMA) instruction of 8085 processor on execution affects a. Zero Flag b. Sign Flag c. Carry Flag d. None of the flags

Answer : B

Description : Application Specific Instruction Set Processor (ASIP)

Answer : An application specific instruction set processor (ASIP) can serve as a compromise between the general purpose processor and single-purpose processors. An ASIP is a Programmable processor ... fetch sequential data memory locations in parallel with other operations to further speed execution.

Description : Which of the following is not true about embedded systems? A. Built around specialized hardware B. Always contain an operating system C. Execution behavior may be deterministic D. All of these E. None of these

Answer : E. None of these 

Description : Why are local variable names beginning with an underscore discouraged? a) they are used to indicate a private variables of a class b) they confuse the interpreter c) they are used to indicate global variables d) they slow down execution

Answer : Answer: a Explanation: As Python has no concept of private variables, leading underscores are used to indicate variables that must not be accessed from outside the class.

Description : When the Testing Principles are useful while building the Software Product? a) During testing b) During execution c) During review d) Throughout life-cycle

Answer : Ans : d

Description : Let the time taken to switch between user mode and kernel mode of execution be T1 while time taken to switch between two user processes be T2. Which of the following is correct? (A) T1 < T2 (B) T1 > T2 (C) T1 = T2 (D) Nothing can be said about the relation between T1 and T2.

Answer : (A) T1 < T2

Description : Code blocks allow many algorithms to be implemented with the following parameters : (A) clarity, elegance, performance (B) clarity, elegance, efficiency (C) elegance, performance, execution (D) execution, clarity, performance

Answer : (B) clarity, elegance, efficiency

Description : Debugger is a program that (A) allows to examine and modify the contents of registers (B) does not allow execution of a segment of program (C) allows to set breakpoints, execute a segment of program and display contents of register (D) All of the above

Answer : (C) allows to set breakpoints, execute a segment of program and display contents of register

Description : WOW32 is a: (A) Win 32 API library for creating processes and threads. (B) Special kind of file system to the NT name space. (C) Kernel - mode objects accessible through Win32 API (D) Special execution environment used to run 16 bit Windows applications on 32 - bit machines.

Answer : (D) Special execution environment used to run 16 bit Windows applications on 32 - bit machines.

Description : Verification: (A) refers to the set of activities that ensure that software correctly implements a specific function. (B) gives answer to the question - Are we building the product right ? (C) requires execution of software (D) both (A) and (B)

Answer : (D) both (A) and (B)

Description : Let Pi and Pj be two processes, R be the set of variables read from memory, and W be the set of variables written to memory. For the concurrent execution of two processes Pi and Pj, which of the following conditions is not true? (A) R(Pi)∩W(Pj)=Φ (B) W(Pi)∩R(Pj)=Φ (C) R(Pi)∩R(Pj)=Φ (D) W(Pi)∩W(Pj)=Φ

Answer : (C) R(Pi)∩R(Pj)=Φ 

Description : In Unix, the command to enable execution permission for file “mylife” by all is ................ (A) Chmod ugo+X myfile (B) Chmod a+X myfile (C) Chmod +X myfile (D) All of the above

Answer : (D) All of the above

Description : In UNIX, processes that have finished execution but have not yet had their status collected are known as ................ (A) Sleeping processes (B) Stopped Processes (C) Zombie Processes (D) Orphan Processes

Answer : (C) Zombie Processes 

Description :

Suppose there are four processes in execution with 12 instances of a Resource R in a system. The maximum need of each process and current allocation are given below:

image
With reference to current allocation, is system safe? If so, what is the safe sequence?
(A) No (B) Yes, P1 P2 P3 P4 (C) Yes, P4 P3 P1 P2 (D) Yes, P2 P1 P3 P4

Answer : (C) Yes, P4 P3 P1 P2

Description : Which of the following is not typically a benefit of dynamic linking? I. Reduction in overall program execution time. II. Reduction in overall space consumption in memory. III. Reduction in overall space consumption on disk. IV. Reduction in the cost of software updates. (A) I and IV (B) I only (C) II and III (D) IV only

Answer : (B) I only 

Description : The content of the accumulator after the execution of the following 8085 assembly language program, is: MVI A, 42H  MVI B, 05H UGC: ADD B DCR B JNZ UGC ADI 25H HLT (A) 82 H (B) 78 H (C) 76 H (D) 47 H

Answer : (C) 76 H

Description : The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B (A) 00H (B) 35H (C) EFH (D) 2FH

Answer : (D) 2FH

Description : In computer processing, ______ selects processes from the pool and loads them into memory for execution. (1) Job Scheduler (2) Resource Scheduler (3) CPU Scheduler (4) Process Scheduler

Answer : Job Scheduler

Description : The section of the CPU that selects, interprects and monitors the execution of program instructions is (1) Memory (2) Register (3) Control unit (4) ALU

Answer : Control unit

Description : The time between program input and output is called (1) Turn around time (2) Waiting time (3) Execution time (4) Delay time

Answer : Turn around time

Description :  ________ is a program that places programs into memory and prepares them for execution. (1) Assembler (2) Compiler (3) Loader (4) Macro processor

Answer : Loader

Description : Define with respect to PLC i) scanning cycle ii) speed of execution.

Answer : Scanning Cycle * It is number of states/steps which the controller follows when it is put in RUN mode. * It is also called as operating cycle and is defined as the number of states ... is referred as a speed of execution. Higher CPU speeds provide faster performance that shortens task time. 

Description : State the function of PLC memory w.r.t. types, speed of execution.

Answer : PLC memory cab be divided into two major types: 1) System memory: a) Executive Memory: The executive is a permanently stored collection of programs that are considered part of the system itself. ... RAM memory is fastest amongst all type of memory. Flash ROM memory is faster than ROM memory. 

Description :

With reference to execution of work explain the following: i) Administrative approval ii) Technical sanctions 

Answer : Administrative approval:  When any government department requires executing a project like network addition or extension work or installation of new project. It requires necessary administrative approval ... designated by government. The sanction given by authority is called technical sanction

Description : In 8085, whenever a signal is received at TRAP terminal, its program execution is transferred to a subroutine on address A) 0000 H B) 002C H C) 0024 H D) 0004 H

Answer : In 8085, whenever a signal is received at TRAP terminal, its program execution is transferred to a subroutine on address 0024 H

Description : In 8085 microprocessor, the value of the most significant bit of the result following the execution of any arithmetic of Boolean instruction is stored in the (1) Carry status flag (2) Auxiliary carry status flag (3) Sign status flag (4) Zero status flag

Answer : In 8085 microprocessor, the value of the most significant bit of the result following the execution of any arithmetic of Boolean instruction is stored in the Sign status flag

Description : Normally, the FPGA resources are used less than 70% because:  a. Routing becomes excessively complicated b. Power issues c. Clock frequency d. Simulation time increases

Answer : Normally, the FPGA resources are used less than 70% because: Routing becomes excessively complicated

Description : List and describe three general approaches to improve designer productivity.

Answer : Automation: The task of using a computer program to replace manual design effort. The program replaces manual design effort. Synthesis. Reuse: The ... correctness/completeness of each design step. Hardware/software co-simulation.

Description : Explain placement, routing, and sizing.

Answer : Placement: The task of placing and orienting every transistor somewhere on IC. Routing: The task of running wires between the transistors without inserting other wires or transistors. ... wires and transistor provide better performance but consume more power and require more silicon area.

Description : A single FSM can be converted to two smaller FSM. Justify.

Description :

Answer : Common computation models: Sequential program model Statements, rules for composing statements, semantics for executing them Communicating process model ... Object-oriented model For breaking complex software into simpler, well-defined pieces

Description : Sketch internal design of 4x3 ROM.

Answer : The internal design of 4x3 ROM

Description : Explain the advantages and disadvantages of using memory I/O and standard I/O.

Answer : Memory mapped I/O and standard I/O are the two methods for communicating microprocessor with peripherals. Processor talks to both memory and peripheral using the same bus.Two ways to talk to a peripheral. ... of standard I/O is no loss of memory addresses to the use as I/O addresses.

Description : Explain parallel and wireless protocols.

Answer : Parallel protocols: PCI bus (Peripheral Components Interconnect): PCI stands for Peripheral Components Interconnect. PCI bus is used as a communication line to transmit signals and data ... provide the basis for wireless network products using the Wi-Fi brand.

Description : Explain memory hierarchy.

Answer : Memory hierarchy: Main memory is large, inexpensive, slow memory stores entire program and data. Cache memory is small, expensive, fast memory stores copy of likely accessed parts of large ... In memory hierarchy the smaller memory is faster and larger memory storage is slower.

Description : Explain memory write ability and storage permanence with suitable diagram.

Answer : Write ability and storage permanence of memories: Write ability is the manner and speed at which memory can be written. Storage permanence is the ability of memory to hold stored bits ... Holds bits after power is no longer supplied. High end and middle range of storage permanence.

Description : Describe different RT level computational and sequential components used to design single function processors.

Answer : RT-level combinational components:- To reduce the complexity in digital logic, combinational components are used, which are more powerful than logic gates.  Such combinational ... during a clock edge. An asynchronous inputs value effects the circuit independent of the clock.

Description :

Build using minimum number of CMOS gates.

  1. Three input NAND gate.
  2. Two input NOR gate
  3. Three input NOR gate
  4. Two input AND gate
  5. Two input OR gate

Answer : Three input NAND gate. Two input NOR gate Three input NOR gate Two input AND gate Two input OR gate

Description : Explain the various steps involved in designing a custom single-purpose processor.

Answer : A single purpose processor is a digital circuit designed to execute exactly one program. It is also known as co-processor, accelerator or peripheral. It contains only ... for small quantities. Performance may not match general-purpose processors for same applications.

Description : If Moor's law continues to hold, predict the approximation number of transistor per leading edge IC in the year. 1.2030 2.2050

Answer : If Moor's law continues to hold, predict the approximation number of transistor per leading edge IC in the year.1.20302.2050

← Prev Question Next Question →
editAsk a Question
...