Cache Mapping Technique

3 Answers

Cache Mapping Technique

•Cache is small, fast and expensive memory.

•This is also use for reducing access time.

•Cache is more closer to CPU than main memory.

•Cache is use to store addresses.

•There are three ways for mapping cache memory.

1.Direct mapping

2.Fully Associative mapping

3.Set-Associative mapping

•These method are use for assigning addresses to cache locations.

1.Direct mapping

•Direct mapping is the easiest.

•It is often use for instruction cache.

•In direct mapping no search is needed.

•But in this method the cache memory is not fully utilized.

•No replacement technique is required in this method of cache mapping.

•In this method only one tag compare is require per access.

•All words stored in cache must have different indices.

2. Fully Associative mapping

•In this type of mapping the tag memory is searched in parallel (Associative) hence it is called Associative mapping.

•In this method cache utilization is very high as compare to other two technique.

•In this method main memory divided into two groups lower order bits for location of a word in block and higher order bits for blocks.

•It is expensive to implement because of cache searching.

•As much comparators as number of tags is required means large number of comparators is required.

•The internal logic compare the incoming address with all the stored addresses.

3. Set-Associative mapping

•Set-Associative mapping have good performance but it is complex.

•Set-Associative mapping is the combination of both direct mapping and fully associative mapping.

•In this method the cache is divided into sets.

•So the search is performed over a cache set in parallel.

•Set-Associative mapping is use in microprocessors.

•It allows limited number of blocks with same index and different tags.

•The incoming tag is compared with all tags of selected sets with the help of comparator.



thumb_up_alt 0 like thumb_down_alt 0 dislike

Cache Mapping Technique






thumb_up_alt 0 like thumb_down_alt 0 dislike

Cache Mapping Technique:-



thumb_up_alt 0 like thumb_down_alt 0 dislike

Related questions

Description : What is the point-to-point drawing technique?

Answer : Those who have a hobby of drawing may have a question - what is the essence of such a popular point-to-point technique? A modern fashionable artist has the right to depict reality and his ... , but in different shades, a picture can be obtained with an impressive effect of volume and delicacy.

Description : List the energy conservation technique in induction motor. 

Answer : Following are the list of energy conservation techniques in electrical motors: 1) Reduction in iron losses by using low loss silicon steel core material laminated to thinner dimension. 2) Using bigger length ... at light load. 13) By rewinding in induction motor 14) By motor survey

Description :

Answer : Energy conservation technique in induction motor by minimizing idle and redundant running of motor: 1) Loss of energy as the no load power drawn is approximately about 12% to 16% of rated ... to unnecessary line losses. 4) Reduction in overall system energy efficiency over period of time.

Description :

Explain energy conservation technique “by improving power quality” for induction motor.

Answer : Energy conservation method in induction motor by improving power quality: Electrical energy can be conserved by improving the power quality. It can be achieved by avoiding voltage unbalance, maintaining ... losses can be minimized by using harmonic filter thus reducing the harmonics in the system.

Description : Explain the pulse width modulation technique for control of AC output voltage.

Description :

Answer : EPROM EEPROM Flash EPROM Normalize cell size is 1. Normalize cell size is about 1 ... and floating gate, which is insulated by a dielectric material. NAND flash memory and NOR flash memory are the two types of flash memory.

Description : In ............. method, the word is written to the block in both the cache and main memory, in parallel. (A) Write through (B) Write back (C) Write protected (D) Direct mapping

Answer : (A) Write through 

Description : Which one of the following methods is best suited for mapping the distribution of different crops as provided in the standard classification of crops in India? (A) Pie diagram (B) Chorochromatic technique (C) Isopleth technique (D) Dot method

Answer : (B) Chorochromatic technique

Description : For mapping purpose, the Earth is divided into two equal halves by an imaginary line called the equator. Likewise, the sky is divided into two equal halves by an imaginary line called the A. celestial equator. B. ecliptic. C. line of nodes. D. zodiac. E. none of the above. Neither are divided equally.

Answer : A. celestial equator.

Description : Requirement Traceability Matrix is a way of doing complete mapping of software a)true b)false

Answer : Ans : true

Description : Using the central point of the classroom communication as the beginning of a dynamic pattern of ideas is referred to as: (A) Systemisation (B) Problem - orientation (C) Idea protocol (D) Mind mapping

Answer : (D) Mind mapping

Description : Which of the following statements is/are incorrect ? (a) Mapping the co-ordinates of the points and lines that form the picture into the appropriate co-ordinates on the device or workstation is known as viewing transformation. (b) The right handed cartesian co-ordinates system in whose coordinates we describe the picture is known as world coordinate system. (c) The co-ordinate system that corresponds to the device or workstation where the image is to be displayed is known as physical device co-ordinate system. (d) Left-handed co-ordinate system in which the display area of the virtual display device corresponds to the unit(|x|) square whose lower left handed corner is at origin of the co-ordinate system, is known as normalized device coordinate system. (A) (a) only (B) (a) and (b) (C) (c) only (D) (d) only

Answer : (D) (d) only

Description : Which one of the following organisations is responsible for publishing topographical sheets? (1) Geological Survey of India (G.S.I.) (2) National Atlas & Thematic Mapping Organisation (N.A. T.M.O.) (3) Indian Meteorological Department (I.M.D.) (4) Survey of India (S.O.I.)

Answer : Survey of India (S.O.I.)

Description : The art and science of map making is called (1) Remote Sensing (2) Cartography (3) Photogrammetry (4) Mapping

Answer : Cartography

Description : Which of the following correctly lists computer memory types from highest to lowest speed? (A) Secondary Storage: Main Memory (RAM); Cache. Memory; CPU Registers (B) CPU Registers; Cache Memory; Secondary Storage; Main Memory (RAM) (C) CPU Registers; Cache Memory: Main Memory (RAM); Secondary Storage (D) Cache Memory; CPU Registers; Main Memory (RAM); Secondary Storage

Answer : Answer: C (CPU Registers > Cache Memory > Main Memory (RAM) > Secondary Storage)

Description : .............. is a type of memory circuitry that holds the computer’s start-up routine. (A) RIM (Read Initial Memory) (B) RAM (Random Access Memory) (C) ROM (Read Only Memory) (D) Cache Memory 

Answer : (C) ROM (Read Only Memory) 

Description : Translation Look-aside Buffer(TLB) is (A) a cache-memory in which item to be searched is compared one-by-one with the keys. (B) a cache-memory in which item to be searched is compared with all the keys simultaneously. (C) an associative memory in which item to be searched is compared one-by-one with the keys. (D) an associative memory in which item to be searched is compared with all the keys simultaneously.

Answer : (D) an associative memory in which item to be searched is compared with all the keys simultaneously.

Description : The virtual address generated by a CPU is 32 bits. The Translation Lookaside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4- cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is (A) 12 bits (B) 15 bits (C) 16 bits (D) 20 bits

Answer : (C) 16 bits Explanation: VirtualAddress = 32 bits PageSize = 4KB = 12 bits therefore : VPNTag = 20 bits, OffsetTag = 12 bits TLBEntryLength = VPNTag = 20 bits TotalTLBEntries = 64, 4-way implies ... therefore : TLBIndex = 4 bits TLBTag = TLBEntryLength - TLBIndex = 20 - 4 = 16 bits

Description : The directory can be viewed as .................... that translates filenames into their directory entries. (A) Symbol table (B) Partition (C) Swap space (D) Cache

Answer : (A) Symbol table

Description : Function of memory management unit is : (A) Address translation (B) Memory allocation (C) Cache management (D) All of the above

Answer : Answer: A

Description : Pipelining improves performance by: (A) decreasing instruction latency (B) eliminating data hazards (C) exploiting instruction level parallelism (D) decreasing the cache miss rate

Answer : (C) exploiting instruction level parallelism

Description : Cache memory acts between (1) CPU and RAM (2) CPU and ROM (3) RAM and ROM (4) CPU and Hard disk

Answer : CPU and RAM 

Description : Cache memory works on the principle of __________ . (1) Locality of data (2) Locality of reference (3) Locality of Memory (4) Locality of Memory & reference

Answer : Locality of reference

Description : In IT, the method for updating the main memory as soon as a word is removed from the cache is called (1) Write – through (2) Write – back (3) Protected – write (4) Cache – write

Answer : Write – back

Description : In IT, associative memory is called as (1) Virtual memory (2) Cache memory (3) Content addressable memory (4) Main memory

Answer : Content addressable memory

Description : What is the name of a memory buffer used to accommodate a speed differential ? (1) Cache (2) Stack Pointer (3) Accumulator (4) Disc

Answer : Cache

Description : The fastest, costlier and relatively small form of storage managed by computer system hardware is : (1) Disk (2) Flash Memory (3) Main memory (4) Cache

Answer : Cache

Description : The most advanced form Of Read Only Memory (ROM) is (1) PROM (2) RAM (3) Cache Memory (4) EEPROM

Answer : EEPROM

Description : State characteristics of L2 cache.

Answer : 1. It is external to the processor core. 2. Same processor can be used with different L2 cache. 3. Larger L2 cache increases the performance of the system. 4. Cache performance can be measured in ... whether the line is in the cache) 7. Miss Penalty = Additional time required because of a miss

Description : State cache memory? Give its types and explain with neat diagram.

Answer : Cache memory: Cache memory is extremely fast memory that is built into a CPU, or located next to it on a separate chip. It supplies the processor with the most frequently requested data ... cache. Later Editions of same processor were introduced with larger L2 cache rather than L3 cache.

Description : As compared to the primary memory, the cache memory of the computer is  (1) Large (2) Cheap (3) Fast (4) slow

Description : The sequence in which the speed is increasing in ascending order  a. RAM  b. Hard disk  c. Cache  d. Thumb Drive/Memory Stick  (1) dbac (2) bdac (3) badc (4) abdc 

Description : The idea of cache memory is based on  (1) The property of locality of reference (2) The heuristic 90-10 rule (3) The fact that only a small portion of a program is referenced relatively frequently (4) All of these

Description : Normally, the FPGA resources are used less than 70% because:  a. Routing becomes excessively complicated b. Power issues c. Clock frequency d. Simulation time increases

Answer : Normally, the FPGA resources are used less than 70% because: Routing becomes excessively complicated

Description : List and describe three general approaches to improve designer productivity.

Answer : Automation: The task of using a computer program to replace manual design effort. The program replaces manual design effort. Synthesis. Reuse: The ... correctness/completeness of each design step. Hardware/software co-simulation.

Description : Explain placement, routing, and sizing.

Answer : Placement: The task of placing and orienting every transistor somewhere on IC. Routing: The task of running wires between the transistors without inserting other wires or transistors. ... wires and transistor provide better performance but consume more power and require more silicon area.

Description : A single FSM can be converted to two smaller FSM. Justify.

Description :

Answer : Common computation models: Sequential program model Statements, rules for composing statements, semantics for executing them Communicating process model ... Object-oriented model For breaking complex software into simpler, well-defined pieces

Description : Sketch internal design of 4x3 ROM.

Answer : The internal design of 4x3 ROM

Description : Explain the advantages and disadvantages of using memory I/O and standard I/O.

Answer : Memory mapped I/O and standard I/O are the two methods for communicating microprocessor with peripherals. Processor talks to both memory and peripheral using the same bus.Two ways to talk to a peripheral. ... of standard I/O is no loss of memory addresses to the use as I/O addresses.

Description : Explain parallel and wireless protocols.

Answer : Parallel protocols: PCI bus (Peripheral Components Interconnect): PCI stands for Peripheral Components Interconnect. PCI bus is used as a communication line to transmit signals and data ... provide the basis for wireless network products using the Wi-Fi brand.

Description : Explain memory hierarchy.

Answer : Memory hierarchy: Main memory is large, inexpensive, slow memory stores entire program and data. Cache memory is small, expensive, fast memory stores copy of likely accessed parts of large ... In memory hierarchy the smaller memory is faster and larger memory storage is slower.

Description : Explain memory write ability and storage permanence with suitable diagram.

Answer : Write ability and storage permanence of memories: Write ability is the manner and speed at which memory can be written. Storage permanence is the ability of memory to hold stored bits ... Holds bits after power is no longer supplied. High end and middle range of storage permanence.

Description : Describe different RT level computational and sequential components used to design single function processors.

Answer : RT-level combinational components:- To reduce the complexity in digital logic, combinational components are used, which are more powerful than logic gates.  Such combinational ... during a clock edge. An asynchronous inputs value effects the circuit independent of the clock.

Description :

Build using minimum number of CMOS gates.

  1. Three input NAND gate.
  2. Two input NOR gate
  3. Three input NOR gate
  4. Two input AND gate
  5. Two input OR gate

Answer : Three input NAND gate. Two input NOR gate Three input NOR gate Two input AND gate Two input OR gate

Description : Explain the various steps involved in designing a custom single-purpose processor.

Answer : A single purpose processor is a digital circuit designed to execute exactly one program. It is also known as co-processor, accelerator or peripheral. It contains only ... for small quantities. Performance may not match general-purpose processors for same applications.

Description : If Moor's law continues to hold, predict the approximation number of transistor per leading edge IC in the year. 1.2030 2.2050

Answer : If Moor's law continues to hold, predict the approximation number of transistor per leading edge IC in the year.1.20302.2050

Description : Compare the annual growth rate of  1.IC capacity 2.Designer productivity.

Answer : Compare the annual growth rate of 1.IC capacity2.Designer productivity.

← Prev Question Next Question →
editAsk a Question